Shrinking the conventional MOSFET (metal oxide semiconductor field effect transistor) beyond the 50 nanometer technology node requires innovations to circumvent barriers due to the fundamental physics that constrain conventional MOSFETs. Continued device shrinkage requires a reduction of gate dielectric thickness. This requirement arises from two different considerations: controlling the short-channel effect, and achieving a high current drive by keeping the amount of charge induced in the channel as large as possible as the power-supply voltage decreases. It is the reduction of the equivalent electrical thickness of the gate dielectric that is important in achieving each of the aforementioned considerations.
One approach for reducing the equivalent electrical thickness of the gate dielectric is to simply reduce the physical thickness of the gate dielectric material. A shortcoming associated with this approach is that the direct tunneling current through the gate dielectric grows exponentially with decreasing physical thickness of the gate dielectric. It is considered that tunneling currents arising from silicon dioxide (SiO2) gate dielectrics thinner than 0.8 nanometers cannot be tolerated, even for high-performance systems. A more favorable approach for reducing the equivalent electrical thickness of the gate dielectric is to use a gate dielectric material that has a high dielectric constant, i.e., a dielectric constant that is higher than about 3.9, the dielectric constant of SiO2. A gate dielectric with a dielectric constant (k) substantially higher than that of SiO2 (kox) will achieve a smaller equivalent electrical thickness (teq) than the SiO2, even with a physical thickness (tphys) larger than that of the SiO2 (tox):teq=(kox/k)tphys.
Replacing the conventional SiO2 gate material with a high-dielectric constant (high-k) dielectric gate material, however, presents other challenges. One challenge associated with the use of high-k gate dielectric material is the inability to sufficiently remove such materials from the non-gate regions where they are not needed. Due to the absence of suitable etch chemistries to remove the high-k gate materials, an aggressive etch and an aggressive and extended over-etch must be used when etching to remove the high-k gate dielectric material, to ensure its complete removal. Such an approach can and often does result in recesses being produced throughout the semiconductor device, including in areas immediately adjacent to the gate region, due to the aggressive etch process. FIG. 1A shows conductive gate 106 formed after an etching process that uses photoresist 110 as a mask. The structure includes optional ARC layer 108 and conductive gate material 106 is formed over high-k gate dielectric 104 and gate oxide 102 formed over surface 112 of substrate 100. After etching the conductive gate material to form conductive gate 106, an etching process is then carried out to remove high-k gate dielectric 104 and gate oxide 102 from regions other than the gate region aligned beneath conductive gate 106. According to the prior art, aggressive etch processes with aggressive and extended overetch steps are required and typically produce receded surface 114 which is receded with respect to original surface 112 by distance 116. Residue of high-k gate dielectric 104 (not shown in FIG. 1A) may also still be present. Conventional methods therefore either produce high-k gate dielectric material residue, recesses formed due to the attack of the material over which the high-k gate dielectric material is formed, or both.
It would therefore be desirable to produce a semiconductor device and provide a method for forming the device with a high-k gate dielectric material and without the above shortcomings.